Synchronization scheme with adaptive reference frequency correction

ABSTRACT

An apparatus and a method provide synchronization of an output signal to a synchronization information. The synchronization is accomplished by providing coupling of a correction control information that controls a signal generator, e.g. a phase locked loop arrangement or a direct digital synthesis arrangement, to its exact frequency to a frequency conversion unit that converts an uncorrected reference frequency to a correct or exact reference frequency. Thereby, the uncorrected reference frequency for the signal generator can be provided by a simple crystal oscillator without any frequency controller. The setting of the signal generator and the frequency conversion unit can be done in a predetermined sequence which enables a user equipment to synchronize its reference frequency to the synchronization information emitted by a communication network.

BACKGROUND

1. Technical Field

The present invention relates to a method and apparatus for providing synchronization of an output signal to a reference signal, to be used for reference frequency synchronization in a mobile terminal, for example.

2. Description of the Related Art

Radio communication devices require generation of stable operating frequencies in order to function properly. Typically, stability has been obtained by using a crystal oscillator as a reference oscillator to provide a reference frequency. Specifically, local oscillators of radio terminals are phase-locked to the reference frequency. However, crystal oscillators by themselves cannot provide a sufficiently constant frequency to meet the frequency stability requirements of the radio terminal. In particular, the output frequency of a crystal oscillator varies over temperature. Additionally, non-linearities in the control path of the reference oscillator may cause frequency deviations.

Radio terminals may also require frequency correction to precisely center a radio transceiver operating frequency onto a counterpart station (e.g. base station) channel frequency. Frequency deviations may also occur due to Doppler shifts caused by movements of the terminal or due to frequency offsets at the counterpart stations (e.g. base stations). This is accomplished using an automatic frequency control (AFC) mechanism which determines an error between the radio transceiver operating frequency and the counterpart station (e.g. base station) channel frequency and applies a correction signal to the crystal oscillator to alter the reference frequency in order to synchronize the frequency of the radio terminal to the counterpart station (e.g. base station). The frequency error is typically obtained in a baseband circuitry where it is based on digital representation. A Digital-to-Analog-Converter (DAC) is used to obtain an analog control signal. This analog control signal is applied to a varactor diode which changes its capacitance in dependence of the applied voltage and therefore the frequency of the crystal oscillator changes, when the capacitance, that builds the resonance circuit varies. An extensive decoupling-network, consisting of several resistors and capacitors is used to obtain proper and especially low-noise performance.

This prior art solution has the disadvantage of additional cost and space and reduced reliability.

Moreover this analog control circuitry has typically no linear control characteristic.

In document WO 03/079548 a method is suggested to generate the exact local oscillator frequency on basis of an uncorrected reference oscillator by altering the division ratio of a Fractional-N-PLL (phase locked loop) circuitry that generates the local oscillator frequency on basis of the reference frequency of an uncorrected reference oscillator. However, in this solution, the exact reference frequency which is needed e.g. for processing of protocol timing and sampling of included Digital-to-Analog-Converters (DACs) and Analog-to-Digital-Converters (ADCs) cannot be provided in the mobile device.

Furthermore, in document U.S. Pat. No. 5,856,766, an exact local oscillator frequency is obtained by an apparatus on the basis of an uncorrected reference frequency by coupling both with a Fractional-N-PLL to which an information containing the initial frequency error of the local-oscillator is supplied to adapt the fractional division ratio in order to minimize the frequency error of the local oscillator. Further mixing or processing frequencies are obtained by providing further integer PLLs on basis of the exact local oscillator. This solution leads to the same problem, that the exact reference frequency itself is not generated, as mentioned above.

Thus, known frequency tracking mechanisms require corresponding control circuitry which involves costs and space, or do not supply any baseband or any output with the exact reference frequency.

BRIEF SUMMARY

It is an object of the present invention to provide an improved synchronization scheme, method and apparatus, by means of which an exact reference frequency can be generated without requiring any additional tracking or control circuitry for the reference frequency oscillator.

This object is achieved by a synchronization apparatus as claimed in claim 1.

Accordingly, synchronization of the reference frequency is accomplished by using a frequency error information which is used for converting the reference frequency to its exact frequency value also for a frequency conversion unit which converts, based on this information, the uncorrected reference frequency of the reference oscillator to the exact reference frequency. Due to the provision of the frequency conversion unit which is controlled by the correction control information derived from the frequency error, the frequency adjustment or tracking function of the output signal can be provided using the frequency conversion unit, so that the frequency of the reference oscillator itself does not have to be changed. Consequently, no external control means for frequency adjustment and/or tracking have to be provided.

Moreover, a strictly linear control characteristic is obtained due to the fact that the frequency conversion unit can be provided independent of any signal generating means, e.g., phase locked loop arrangement. Any modulations introduced in the voltage controlled oscillator VCO of the phase locked loop arrangement have no impact on the exact reference frequency that is the output signal, because the arrangement realizes decoupling.

Additionally, the correction control information is independent from the actually used radio channel, so that fast synchronization can be obtained even after switching to a new channel. The same frequency divider offset is, besides receive channels, also applicable for transmission channels. Then, the exact reference frequency is the reference for the generation of the transmit signal when a transmit section is provided.

As the exact reference frequency is not derived from the output signal of the PLL arrangement, the PLL arrangement does not have to be active when the exact reference frequency is required. This is advantageous in that a reduced current consumption can be achieved which will increase stand-by times.

The synchronization error may be determined based on a synchronization error between the output signal and the conversion signal generated by the signal generating means. Alternatively, the synchronization error may be determined based on a synchronization error between the output signal and the synchronization information.

The reference oscillator used for generating the uncorrected reference frequency may be a crystal or MEMS (Micro-Electro-Mechanical System) oscillator, and may be a non-controllable fixed-frequency oscillator. The predetermined nominal division ratio can be derived from the ratio between the nominal channel frequency, which is defined by the corresponding communication system, and the nominal reference frequency.

Furthermore, the control means may be connected to a programming interface for setting the channel control information and the correction control information. A change of the frequency can thus be achieved by reprogramming the phase locked loop arrangement and the frequency conversion means using the programming interface.

The correction control information may comprise a frequency correction addend which is independent from the transmission channel, and an independent conversion factor which is also independent from the transmission channel. Then, the frequency conversion means may comprise a series combination of a multiplier means for multiplying the reference frequency by a multiplication factor determined on the basis of the frequency correction addend and the conversion factor and a divider means for dividing the multiplied reference frequency by a division factor determined on the basis of the independent conversion factor. Additionally, the frequency conversion means may comprise filter means for limiting the spectral composition of the output of the divider means. Thereby, the spectral purity of the output signal of the frequency conversion means can be enhanced.

The multiplier means may be e.g. a kind of Fractional-N-PLL, integer-PLL, or other type of multiplication means.

The divider means may be e.g. a kind of integer divider, Fractional-N divider, integer divider or other type of division means.

The control means may be arranged to set the independent conversion factor to obtain an integer value of the multiplication factor. Alternatively the control means may be arranged to set the independent conversion factor to obtain an integer value of the division factor. As an substitute to the above programming option, the independent conversion factor can be hardwired in the apparatus, so that programming thereof is not required.

Additionally, switching means may be provided for connecting either the uncorrected reference frequency or the output of the frequency conversion means to an output of the synchronization apparatus. Thereby, at an initial start of the synchronization procedure, the uncorrected reference frequency may be switched by the switching means to a controlling unit for activation and initialization.

As an example, the output signal may be supplied to a baseband processing unit which comprises calculating means for calculating the synchronization error based on a frequency offset. The synchronization can thus be achieved by calculating the frequency offset at the baseband processing unit and setting the frequency correction addend for next step based thereon, e.g. via the programming interface.

Further advantageous modifications are defined in the dependent claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The present invention will now be described based on a preferred embodiment with reference to the accompanying drawings, in which:

FIG. 1 shows a schematic block diagram of a synchronization scheme according to the present invention;

FIG. 2 shows a schematic block diagram of a mobile terminal with a synchronization mechanism according to the preferred embodiment in a situation directly after switching on the arrangement;

FIG. 3 shows the mobile terminal of FIG. 2 in a situation after a synchronized state has been reached; and

FIG. 4A-4B shows a flow diagram relating to a transfer procedure from the initial state indicated in FIG. 2 to the synchronized state indicated in FIG. 3.

DETAILED DESCRIPTION

The preferred embodiment will now be described based on a synchronization of a mobile terminal to a synchronization information or synchronization signal emitted by a cellular network.

FIG. 1 shows a schematic block diagram indicating the synchronization mechanism underlying the preferred embodiment. The synchronization of the reference frequency in the mobile terminal or mobile user equipment is accomplished by deriving from a control information of a divider 8 of a phase locked loop (PLL) circuitry 30 a further control information for a frequency conversion unit 90. The PLL circuitry 30 is supplied with an uncorrected reference oscillator signal B. This uncorrected reference oscillator signal B for the phase locked loop circuitry 30 is generated by a simple crystal oscillator 2 having no means or circuitry for frequency control. The setting of the divider 8 and the frequency conversion unit 90 and their configuration is performed by a control unit or mechanism 40. This follows a certain sequence which enables the user equipment to synchronize its generated reference frequency f_(ref) to a frequency information (N.k)*f_(ref) or a frequency correction or synchronization information received from the cellular network by a corresponding receiver unit 50 to which the signal generated by the phase locked loop circuitry 30 is supplied e.g. for mixing or other synchronized receiving purposes.

The receiver unit 50 generates a digital receiving signal DRS which is further processed in a subsequent unit (not shown). As indicated in FIG. 1, the uncorrected reference frequency of the reference oscillator signal B generated by the crystal oscillator 2 has a frequency error ε which is compensated in the synchronized output signal D by a corresponding resulting frequency conversion factor set at the frequency conversion unit 90 by the control unit 40. Thereby, an output signal D with a synchronized or corrected exact reference frequency f_(ref) can be obtained without requiring any adjustment of the crystal oscillator 2 itself. It is to be noted here, that the crystal oscillator 2 may be replaced by any suitable reference oscillator which generates a fixed frequency.

In the following, the above synchronization mechanism will be described in more detail based on a so-called “zero-IF-receiver” arrangement, which is a super heterodyne (superhet) receiver with an intermediate frequency (IF) of 0 Hz. This means that the received high frequency or radio frequency (RF) signal is directly converted into the baseband frequency, e.g., by a corresponding frequency conversion circuit. However, it is to be noted that the principle of the proposed synchronization mechanism can be applied to other receiver architectures as well, such as for example other superhet principles involving a non-zero IF.

In the figures, only those connections or control lines, respectively, are shown and indicated by corresponding symbols, which are relevant for the description of the preferred embodiment.

According to FIG. 2, an arrangement is proposed for receiving and synchronizing to a synchronization information emitted by a network. To achieve this, a synchronization signal H is received by means of an antenna 1, is converted by a subsequent receiver arrangement 10 into a baseband frequency, and is decoded and evaluated in a subsequent baseband processing unit 20. For frequency conversion, a mixer 12 is arranged in the receiver arrangement 10 following the connected antenna 1. The mixer 12 is followed by a low pass filter 13 for band limitation of the converted receiving signal, and by an analog-to-digital converter 14 for converting the converted receiving signal into a digital receiving signal. The conversion signal C for the mixer 12 is generated by a connected voltage-controlled oscillator 7, which is part of a phase locked loop arrangement 30. The phase locked loop arrangement 30 comprises further a PLL divider 8, for example a fractional-N-frequency divider, a phase-frequency comparator 5, and a loop filter 6.

Additionally, a reference crystal oscillator 2 serves to generate a reference oscillator signal B with an uncorrected reference frequency, which is used as phase comparison frequency supplied to the phase-frequency comparator 5. The phase locked loop arrangement 30 serves to converge the frequency of the frequency-divided signal E to the uncorrected reference frequency of the reference oscillator signal B when the steady state has been reached.

The reference crystal oscillator 2 does not require any control circuit for frequency variation or frequency tracking, respectively. Here, the required exact reference frequency is designated by f_(ref) and its absolute precision is predefined by the respective communication system. In contrast thereto, the uncorrected reference frequency of the reference oscillator signal B of the reference crystal oscillator 2 deviates from the exact reference frequency f_(ref) by a reference frequency error ε.

According to the preferred embodiment, a frequency conversion unit 90 is connected to the output of the crystal-oscillator 2. The frequency conversion unit 90 converts the uncorrected reference frequency of the reference oscillator signal B to the corrected frequency of the output signal D of the frequency conversion unit 90. This conversion is determined by the resulting frequency conversion factor (κ).

$\begin{matrix} {\kappa = \frac{f_{D}}{f_{B}}} & \left\{ 1 \right\} \end{matrix}$

where f_(D) designates the corrected frequency of the output signal D and f_(B) designates the uncorrected reference frequency of the reference oscillator signal B. In the same manner in the following, all symbols being f[index signal name] designate the frequency of the signal. The frequency conversion unit 90 consists of a series combination of a coupled multiplier 91, a coupled divider 92 and an output signal filter 93. The coupled multiplier 91 converts the reference oscillator signal B to a converted frequency signal I. And the coupled divider 92, in combination with the subsequent output signal filter 93, converts the converted frequency signal I to the output signal D of the frequency conversion unit 90.

The function of the output signal filter 93 is to limit the spectral composition and to limit the noise bandwidth of the output signal of the coupled divider 92. So, the spectral purity of the output signal D of the frequency conversion unit 90 is enhanced. The filter characteristic of the output signal filter 93 may be a bandpass or lowpass characteristic.

The division factor of the PLL-divider 8 is a combination of two logical division ratios, a nominal division ratio N.k and a correction division ratio (1−σ). In particular, the nominal division ratio N.k can be derived from the ratio of the mobile radio channel frequency of the received signal to the nominal reference frequency. Whereas the correction division ratio (1−σ), in particular the frequency correction addend σ, is used to obtain the exact needed frequency for the voltage controlled oscillator 7. This frequency relation between the frequency-divided signal E and the conversion signal C can be expressed as follows:

$\frac{f_{E}}{f_{C}} = \frac{1}{\left( {N \cdot K} \right)*\left( {1 - \sigma} \right)}$

A last-programmed indexed reference designator frequency correction addend σ⁻¹, is used to distinguish from the frequency correction addend σ₊₁ for the next step and to bring both in a timely relationship.

Additionally, the frequency multiplication factor μ of the coupled multiplier 91 consists of the above mentioned correction division ratio (1−σ) supplemented by an independent conversion factor ρ according to following equation {2}.

$\begin{matrix} {\mu = {\frac{f_{I}}{f_{B}} = {\rho*\left( {1 - \sigma} \right)}}} & \left\{ 2 \right\} \end{matrix}$

The frequency division factor ζ of the coupled divider 92 consists of the above mentioned independent conversion factor ρ that is also part of the programming of the coupled multiplier 91. This is expressed in the following equation {3}:

$\begin{matrix} {\zeta = {\frac{f_{D}}{f_{I}} = \frac{1}{\rho}}} & \left\{ 3 \right\} \end{matrix}$

The dividing ratios or conversion factors N.k, (1−σ) and ρ are set by a programming interface 11 which is connected to the PLL divider 8 via a control connection F for programming of the nominal division ratio N.k, and to the PLL divider 8 and the coupled multiplier 91 via another control connection G for programming of the frequency correction addend σ, and to the coupled multiplier 91 and the coupled divider 92 via a further control connection K for programming of the independent conversion factor ρ. The setting procedure of the programming interface 11 is controlled by a radio controller 16 arranged in the baseband processing unit 20.

Furthermore, a selection switch 3 is controlled by the programming interface 11. The selection switch 3 either connects the reference oscillator signal B of the reference crystal oscillator 2 or the output signal D of the frequency conversion unit 90 to the baseband processing unit 20, particularly to a baseband receiver 4 provided in the baseband processing unit 20.

The baseband receiver 4 receives the digital receiving data from the analog-to-digital converter 14 of the receiver arrangement 10 for post-processing and decoding. A frequency offset calculator 15 is connected to the baseband receiver 4 where the synchronization information originally emitted by the network is decoded. The frequency offset calculator 15 calculates a frequency offset information A based on the last setting of the nominal division ratio N.k.

In mathematical terms, the frequency offset information A corresponds to the difference between the frequency f_(H) of the synchronization information H and the frequency f_(C) of the conversion signal C applied to the mixer 12 for conversion to the baseband frequency. This can be expressed as follows:

$\begin{matrix} {A = {f_{C} - f_{H}}} & \; \\ {f_{C} = {\left( {N \cdot k} \right)*\left( {1 - \sigma_{- 1}} \right)*\left( {f_{ref} + ɛ} \right)}} & \; \\ {f_{H} = {\left( {N \cdot k} \right)*f_{ref}}} & \; \\ {A = {\left( {N \cdot k} \right)*\left\lbrack {ɛ - {\sigma_{- 1}*\left( {f_{ref} + ɛ} \right)}} \right\rbrack}} & \left\{ 4 \right\} \\ {ɛ = \frac{\frac{A}{\left( {N \cdot k} \right)} + {\sigma_{- 1}*f_{ref}}}{1 - \sigma_{- 1}}} & \left\{ 5 \right\} \end{matrix}$

For achieving and maintaining the conversion signal C generated by the voltage-controlled oscillator 7 at its exact frequency, the frequency correction addend σ of the division factor of the PLL divider 8 is continuously tracked based on the obtained frequency offset information A.

As this continuously tracked frequency correction addend σ is also updated in the coupled multiplier 91, the generated output signal D will have the exact reference frequency, even when the uncorrected reference frequency of the reference oscillator signal B drifts, caused by e.g. temperature variations.

The situation shown in FIG. 2 corresponds to a state directly after switching on the power supply to the arrangement. At the beginning of the synchronization process, the uncorrected reference frequency of the reference oscillator signal B of the reference crystal oscillator 2 with its reference frequency error ε is connected via the selection switch 3 to the baseband processing unit 20, so that the baseband processing unit 20 can start up. This is required due to the fact that the frequency conversion unit 90 does not deliver an output signal D before the radio controller 16 of the baseband processing unit 20 has been initialized.

Afterwards, the nominal division ratio N.k of the PLL divider 8 is programmed as a channel control information via the control connection F, and the frequency correction addend σ of the PLL divider 8 and the coupled multiplier 91 is programmed to zero via the control connection G (i.e., σ=0), and the independent conversion factor ρ of the coupled multiplier 91 and the coupled divider 92 is programmed to its constant value. Thereby, in the steady state of the phase locked loop arrangement 30, the frequencies of the signals B, D, and E are all equal to the value f_(ref)+ε.

The conversion signal C required for frequency conversion at the mixer 12 is obtained from the uncorrected reference frequency of the reference oscillator signal B, which is multiplied by the nominal division ratio N.k and the correction division ratio (1−σ) of the PLL divider 8 by using the phase locked loop arrangement 30 consisting of blocks 5, 6, 7 and 8, while the last-programmed frequency correction addend σ⁻¹ is set to zero and therefore the correction division ratio (1−σ⁻¹) is one. Thus, the frequency of the conversion signal C amounts to: f _(C)=(N.k)*(f _(C)+ε).

The frequency error information A obtained at the frequency offset calculator 15 of the baseband processing unit 20 amounts to (N.k)*ε. This corresponds to the reference frequency error ε at the reference crystal oscillator 2 multiplied by the nominal division ratio (N.k).

The contributors to the frequency multiplication factor μ especially the independent conversion factor ρ can be chosen in order that the frequency multiplication factor μ results in an integer number.

Alternatively, the resulting frequency conversion factor κ especially the independent conversion factor ρ can be chosen in order that the resulting frequency conversion factor κ results in an integer number.

In general, the independent conversion factor ρ need not necessarily be programmed. It can also be hardwired.

For principal functionality the independent conversion factor ρ can be of every rational or irrational number. As an example, the independent conversion factor ρ can be chosen to be significant higher than “1” in order to obtain best performance of output signal with respect to noise and spurs generated by the frequency conversion unit 90.

Ultimate target of the arrangement according to the preferred embodiment is that the corrected reference frequency of the output signal D of the frequency conversion unit 90 and thus the frequency forwarded to the baseband processing unit 20 exactly corresponds to the exact reference frequency, i.e., the frequency of the output signal D amounts to f_(ref).

Furthermore, it shall be achieved that the mixer 12 is operated by the exact nominal conversion frequency, such that the frequency of the conversion signal C shall amount to f_(ref)*(N.k). In vie/w of the fact that the signals C and B=E are linked by the division ratio (N.k)*(1−σ) of the PLL-divider 8, the frequency of the conversion signal C amounts to (N.k)*(1−σ)*(f_(ref)+ε).

This leads to the following expressions, when synchronization of the signal C is forced: f _(C)=(N.k)*(1−σ)*f _(E) in general f _(C) =f _(ref)*(N.k) in case of synchronization

$\begin{matrix} {{f_{ref}*\left( {N \cdot k} \right)} = {\left( {N \cdot k} \right)*\left( {1 - \sigma} \right)*\left( {f_{ref} + ɛ} \right)}} & \; \\ {f_{ref} = {\left( {1 - \sigma} \right)*\left( {f_{ref} + ɛ} \right)}} & \; \\ {\sigma_{+ 1} = \frac{ɛ}{f_{ref} + ɛ}} & \left\{ 6 \right\} \\ {ɛ = {\frac{\sigma_{- 1}}{1 - \sigma_{- 1}}*f_{ref}}} & \left\{ 7 \right\} \end{matrix}$

In the above equations {6} and {7}, it is advantageous that the calculations from the last-programmed frequency correction addend σ⁻¹ to the frequency error ε and from frequency error ε to the next-step frequency correction addend σ₊₁, that are required for generation and maintaining of the exact reference frequency of the output-signal D do not depend on the nominal division ratio N.k and thus do not depend on the selected mobile radio channel. This means that synchronization can be upheld even during a change of the mobile radio channel without reprogramming the frequency correction addend σ.

It shall be mentioned that all multiplicative combinations of division, respectively multiplication ratios like in PLL-divider 8 and coupled multiplier 91 might only be for logical and software-programming representation. This means that these parts might be physically realized as one Fractional-N divider (block 8) respectively multiplier (block 91) with one fractional division ratio.

FIG. 3 shows the block diagram of FIG. 2 in a situation when synchronization has been reached. This means that the complete apparatus generates the exact reference frequency of the output signal D that is fed through the switch 3 to the baseband processing unit 20 and possibly to some other parts e.g. a GPS unit that requires this exact reference frequency. Also, the conversion signal C is at its exact frequency.

As explained above in connection with the ultimate target, the reference frequency error ε can be derived, using equation {5} at the baseband processing unit 20. Therefore, the frequency offset information A is processed, using equation {5}, due to the fact that the nominal division ratio N.k is known by the set radio channel and the last-programmed frequency correction addend σ⁻¹ is known from the last programming and therefore valid for the conditions at which the actual frequency offset information A was caused. Here, σ⁻¹ is either 0 in the initial state or known from a previous setting. Thus, the frequency correction addend σ₊₁ for the next step of the PLL-divider 8 and subsequent steps can be programmed or set according to equation {6}.

After the phase locked loop arrangement 30 has reached its steady state, the frequency of the conversion signal C exactly corresponds to the value f_(ref)*(N.k), which corresponds to the exact conversion frequency of the mixer 12. As the frequency of the conversion signal C comprises the two components (N.k)*f_(ref) and (N.k)*ε, the second component which corresponds to the frequency offset information A thus reaches zero value at this stage, i.e. (N.k)*ε=0. The programming interface 11 controls the selection switch 3 to connect the output signal D of the frequency conversion unit 90 to the baseband processing unit 20. This means that the exact reference frequency f_(ref) is used in the receiver arrangement 10 as well as in the baseband processing unit 20, independent from the reference frequency error ε of the uncorrected reference frequency of the reference oscillator signal B.

Due to for example temperature changes within the mobile terminal, the reference frequency error ε changes with time. Thus, during operation, the frequency offset information A of the frequency offset calculator 15 may temporarily deviate from zero. In response to this deviation, a reprogramming of the frequency correction addend σ is performed in the PLL divider 8 and in the coupled multiplier 91 in order to set the frequency offset information A to zero, which corresponds to a reference frequency tracking function for compensating any reference frequency error ε.

In the description of the preferred embodiment, any temporary changes of the synchronization information emitted by the network and received by the mobile terminal, which may be caused by Doppler effects and frequency deviations due to frequency offsets at the counterpart station (e.g. base station) cannot be distinguished from changes of the uncorrected reference frequency and are regarded to be represented by the reference frequency error ε.

A benefit of this arrangement is that, after the frequency correction addend is obtained, the RF section build by the phase locked loop arrangement 30 and the receiver unit 50 need no longer be active for generation of the exact reference frequency of the output signal D. This is valid as long as the frequency error ε does not drastically change. This helps to save current or power and therefore to increase stand-by time.

A further benefit of this arrangement is that the voltage controlled oscillator 7 can be modulated without coupling or transferring frequency changes to the output signal D.

FIG. 4 shows a schematic flow diagram relating to the change or transfer procedure from the initial state according to FIG. 2 to the synchronized state according to FIG. 3. In particular, FIG. 4 depicts a way in which the reference frequency is tracked during the operation of the mobile terminal.

In step S100, the mobile terminal is switched on for reference frequency synchronization. Then, in step S101 the selection switch 3 connects the reference oscillator signal B of the reference crystal oscillator 2 to the baseband processing unit 20 for activation thereof. Subsequently, in step S102, the PLL divider 8 is set or programmed to the nominal division ratio N.k, and the correction division ratio (1−σ) with frequency correction addend (σ) equal to 0 is set to the PLL divider 8 and the coupled multiplier 91, and the independent conversion factor ρ is set to the coupled multiplier 91 and the coupled divider 92 at the beginning. In step S103, the selection switch 3 is switched and now connects the output signal D of the frequency conversion unit 90, which frequency at this time corresponds to the uncorrected reference frequency of the reference oscillator signal B of the reference crystal oscillator 2, to the baseband processing unit 20. In step S104, the voltage-controlled oscillator 7 generates a conversion signal C for the mixer 12, which is still erroneous at this initial point in time.

In step S105, the frequency error information A is generated by the frequency error calculator 15. In the following decision step S106, it is checked whether the frequency offset information A is zero or not. If the frequency offset information A is zero, the procedure jumps to step S110, where a synchronized operating state is assumed and a waiting time with conditions that depend on decisions made in step S111 is started. Details and following steps are given within the description of the other branch of the flow diagram.

If it is determined in step S106 that the frequency offset information A is not equal zero it is proceeded with step S107. As indicated in step S107, the reference frequency error ε of the uncorrected reference frequency of the reference oscillator signal B can be obtained by evaluating the frequency offset information A obtained at the frequency offset calculator 15 by applying equation {5}.

The frequency correction addend σ₊₁ required for next synchronization step is determined by using equation {6} and is set at the PLL divider 8 and coupled-multiplier 91 in step S108. Then, in step S109, the voltage-controlled oscillator 7 changes the frequency of the conversion signal C to the exact conversion frequency of the mixer 12 and the frequency conversion unit 90 produces the output signal D with the exact reference frequency. Consequently in the following step S110 a synchronized operating state is entered.

In the following decision step S111, it is checked whether operation of the RF section (phase locked loop arrangement 30 and receiver unit 50) is necessary for the next waiting time. If so, the waiting time is initiated in step S113 and after the waiting time, the procedure jumps back to step S105.

If it is determined in step S111 that operation of the RF section is not necessary, the RF section is switched of in step S112 and the following step is step S113, which initiates a waiting time. After expiry of the waiting time, a decision is made in step S114 whether a new synchronization is wanted. If not, the procedure jumps back to step S113 and a new waiting cycle is initiated. If a new synchronization is wanted, the RF section is switched on in step S115 and the procedure jumps back to step S105.

In general, the present invention provides the advantage that physical, discrete, analog circuits for frequency tracking at the reference crystal oscillator circuit, such as tuning elements filter and decoupling circuits, can be dispensed with, which leads to savings in costs and space.

Besides, there is the advantage that the RF section can be switched off, after the correction control information was generated.

A further benefit is, that the output signal is decoupled from the voltage-controlled oscillator 7. So the voltage controlled oscillator 7 can be modulated, without having any influence on the spectral quality of the exact reference frequency of the output signal D as output signal.

Finally, the above preferred embodiment as depicted in FIGS. 2, 3 and 4 provides the advantage that the frequency correction addend σ is independent from the set mobile radio channel and independent from the operation as receiver or transmitter.

In summary, an apparatus and method for providing synchronization of an output signal D to a synchronization information or synchronization signal H has been described, wherein the synchronization is accomplished by providing coupling of a correction control information that controls a signal generating means, such as a phase locked loop arrangement 30 or a direct digital synthesis arrangement, to its exact frequency to a frequency conversion unit 90 that converts an uncorrected reference frequency to a correct or exact reference frequency. Thereby the uncorrected reference frequency, provided by a simple crystal oscillator 2 without any means for frequency control, can be used in the radio communication apparatus. This is achieved by the proposed apparatus and method, that generates the output signal D with an exact reference frequency that is used internally in the baseband processing unit 20 and moreover can be fed to external devices. Furthermore, with the present apparatus and method, a conversion signal C is generated on its exact frequency, that is used in the receiver arrangement 10, especially in mixer 12. The setting of the phase locked loop arrangement 30 and the frequency conversion unit 90 can be done in a predetermined sequence which enables a user equipment to synchronize its reference frequency to a received frequency correction information emitted by a communication network.

It is noted that the present invention is not restricted to the above preferred embodiment and generalized embodiment, but can be applied in any receiver and/or receiver-transmitter arrangement, such as for example super heterodyne receivers, where a clock frequency, reference frequency or other control frequency, which is derived in a terminal device or other device, is synchronized to a comparison frequency derived from or contained in a synchronization information broadcast from a network or made available by other communication media. As alternative to the phase locked loop arrangement 30, the conversion signal C can also be generated by use of other signal generating means, like for example direct digital synthesis arrangement. Here, also, in an earlier step the channel control information is used for generation of the uncorrected conversion signal C. In a later step, the channel control information together with the correction control information is used in order to obtain generation of the exact conversion signal C.

The synchronization error does not necessarily have to be derived from the difference between the frequency f_(H) of the synchronization information H and the frequency f_(C) of the conversion signal C applied to the mixer 12 for conversion to the baseband frequency. As an alternative option, the synchronization may be derived from a comparison of the frequency f_(H) of the synchronization information H with the frequency f_(D) of the output signal D.

As a further alternative option, the synchronization may be derived from a comparison of the frequency f_(H) of the synchronization information H with the frequency f_(B) of the reference oscillator signal B.

Specific examples for implementing the present invention are terminal devices for use in the Global System for Mobile communication (GSM), the Universal Mobile Communications System (UMTS), Code Division Multiple Access (CDMA) systems, wireless networks such as those specified in IEEE 802.11, IEEE 802.15, IEEE 802.16, Digital Enhanced Cordless Telephone (DECT) systems, Bluetooth systems, and/or any other radio communication standard. The preferred embodiment may thus vary within the scope of the attached claims. 

1. A synchronization apparatus, comprising: a frequency converter configured to convert, based on correction control information, a reference frequency into a corrected reference frequency for processing a received synchronization signal; and a frequency correction controller configured to generate the correction control information based on a determined synchronization error with respect to said synchronization signal.
 2. An apparatus according to claim 1, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between an output signal, having the corrected reference frequency, and said synchronization signal.
 3. An apparatus according to claim 1, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between said reference frequency and a frequency of said synchronization signal.
 4. An apparatus according to claim 1, further comprising a phase lock loop configured to receive said reference frequency and generate a conversion signal, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between said conversion signal and said synchronization signal.
 5. An apparatus according to claim 4, wherein said phase lock loop is configured to set an initial division ratio based on channel control information, and set a frequency correction division ratio based on said correction control information.
 6. An apparatus according to claim 5, further comprising a programming interface coupled to the frequency correction controller and configured to provide said correction control information to said frequency converter and said channel control information to said phase lock loop.
 7. An apparatus according to claim 1, wherein said frequency converter comprises: a multiplier configured to multiply said reference frequency by a multiplication factor determined based on a frequency correction addend, which is derived from said correction control information, and an independent conversion factor; and a divider configured to divide said multiplied reference frequency by a division factor based on said independent conversion factor.
 8. An apparatus according to claim 7, wherein said frequency correction controller is configured to set said independent conversion factor to obtain an integer value of said multiplication factor.
 9. An apparatus according to claim 1, further comprising a switch configured to selectively supply said reference frequency and an output of said frequency converter to a baseband processing unit coupled to said frequency correction controller.
 10. A radio communication device comprising: an antenna configured to receive a synchronization signal; and a synchronization apparatus that includes: a frequency converter configured to convert, based on correction control information, a reference frequency into a corrected reference frequency for processing the synchronization signal; and a frequency correction controller configured to generate the correction control information based on a determined synchronization error with respect to said synchronization signal.
 11. A device according to claim 10, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between an output signal, having the corrected reference frequency, and said synchronization signal.
 12. A device according to claim 10, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between said reference frequency and a frequency of said synchronization signal.
 13. A device according to claim 10, wherein the apparatus includes a phase lock loop configured to receive said reference frequency and generate a conversion signal, wherein said frequency correction controller is configured to determine the synchronization error based on a synchronization error between said conversion signal and said synchronization signal.
 14. A device according to claim 13, wherein said phase lock loop is configured to set an initial division ratio based on channel control information, and set a frequency correction division ratio based on said correction control information.
 15. A device according to claim 14, wherein the apparatus includes a programming interface coupled to the frequency correction controller and configured to provide said correction control information to said frequency converter and said channel control information to said phase lock loop.
 16. A device according to claim 15, wherein the phase lock loop is configured to derive the initial division ratio from a ratio between a frequency of the synchronization signal and the reference frequency.
 17. A device according to claim 10, wherein said frequency converter comprises: a multiplier configured to multiply said reference frequency by a multiplication factor determined based on a frequency correction addend, which is derived from said correction control information, and an independent conversion factor; and a divider configured to divide said multiplied reference frequency by a division factor based on said independent conversion factor.
 18. A device according to claim 17, wherein said frequency correction controller is configured to set said independent conversion factor to obtain an integer value of said multiplication factor.
 19. A device according to claim 10, wherein the apparatus includes a switch configured to selectively supply said reference frequency and an output of said frequency converter to a baseband processing unit coupled to said frequency correction controller. 